A minor hitch running RISC OS code on ARMLinux
Here's the thing: RISC OS modules, libraries and, occasionally, even applications switch merrily between USR and SVC mode at will. There's even a system call, OS_EnterOS, which exits with your application running in SVC mode, no questions asked.
The problem is that at least one instruction to return to user mode (MSR CPSR_c, r1) is still a legal instruction in user mode (i.e. its execution isn't flagged as an exception), so ROLF can't detect that it should switch the "banked" registers it emulates.
One solution might be to jump to the code while in SVC mode but, even if that works, there would be a hole in the Linux security model big enough to fly a fleet of A380s through.